DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

21.6.4

The Trigger Status register is used by software to determine if the GPIO triggered a

GPE. This only applies to GPIOs set as input and with one or both of the Trigger modes

enabled.

Register Map

Figure 46. Legacy GPIO Register Map

Legacy PCI

Header

D:31,F:0

IO Space

GPIO_BASE_

ADDRESS

Legacy GPIO

Registers

21.6.5 IO Mapped Registers

Table 118. Summary of I/O Registers—GBA

Offset

Start

0h

4h

8h

Ch

10h

14h

18h

1Ch

20h

24h

28h

2Ch

Offset End

Register ID—Description

3h

7h

Bh

Fh

13h

17h

1Bh

1Fh

23h

27h

2Bh

2Fh

“Core Well GPIO Enable (CGEN)—Offset 0h” on page 833

“Core Well GPIO Input/Output Select (CGIO)—Offset 4h” on page 833

“Core Well GPIO Level for Input or Output (CGLVL)—Offset 8h” on page 834

“Core Well GPIO Trigger Positive Edge Enable (CGTPE)—Offset Ch” on page 834

“Core Well GPIO Trigger Negative Edge Enable (CGTNE)—Offset 10h” on page 834

“Core Well GPIO GPE Enable (CGGPE)—Offset 14h” on page 835

“Core Well GPIO SMI Enable (CGSMI)—Offset 18h” on page 835

“Core Well GPIO Trigger Status (CGTS)—Offset 1Ch” on page 836

“Resume Well GPIO Enable (RGEN)—Offset 20h” on page 836

“Resume Well GPIO Input/Output Select (RGIO)—Offset 24h” on page 837

“Resume Well GPIO Level for Input or Output (RGLVL)—Offset 28h” on page 837

“Resume Well GPIO Trigger Positive Edge Enable (RGTPE)—Offset 2Ch” on page 837

Default

Value

00000003h

00000003h

00000000h

00000000h

00000000h

00000000h

00000000h

00000000h

0000003Fh

0000003Fh

00000000h

00000000h

Intel® Quark SoC X1000

DS

832

October 2013

Document Number: 329676-001US

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