DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:2
0b
RO
Reserved (RSV): Reserved.
Trigger Enable (TE): When set, the corresponding GPIO, if enabled as input via
1:0
0b
RW
CGIO.IO[n], will cause an NMI/SMI/SCI when a 1 to 0 transition occurs. When cleared,
the GPIO is not enabled to trigger an NMI/SMI/SCI on a 1 to 0 transition. This bit has no
meaning if CGIO.IO[n] is cleared (i.e. programmed for output)
21.6.5.6
Core Well GPIO GPE Enable (CGGPE)—Offset 14h
Access Method
Type: I/O Register
(Size: 32 bits)
CGGPE: [GBA] + 14h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:2
0b
RO
Reserved (RSV): Reserved.
1:0
0b
RW
Enable (EN): When set, the corresponding GPIO, is enabled to generate an SCI and bit
14 of GPE0 Status register of GPE0 Block will be set.
21.6.5.7
Core Well GPIO SMI Enable (CGSMI)—Offset 18h
Access Method
Type: I/O Register
(Size: 32 bits)
CGSMI: [GBA] + 18h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
835
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