DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
21.6.5.17 Core Well GPIO NMI Enable (CGNMIEN)—Offset 40h
Access Method
Type: I/O Register
(Size: 32 bits)
CGNMIEN: [GBA] + 40h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:2
0b
RO
Reserved (RSV): Reserved.
1:0
0b
RW
Enable (EN): When set, the corresponding GPIO, is enabled to generate an NMI.
21.6.5.18 Resume Well GPIO NMI Enable (RGNMIEN)—Offset 44h
Access Method
Type: I/O Register
(Size: 32 bits)
RGNMIEN: [GBA] + 44h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:6
0b
RO
Reserved (RSV): Reserved.
5:0
0h
RW
Enable (EN): When set, the corresponding GPIO, is enabled to generate an NMI.
Intel® Quark SoC X1000
DS
840
October 2013
Document Number: 329676-001US
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