DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

Table 118. Summary of I/O Registers—GBA (Continued)

Offset

Start

30h

34h

38h

3Ch

40h

44h

Offset End

Register ID—Description

33h

“Resume Well GPIO Trigger Negative Edge Enable (RGTNE)—Offset 30h” on page 838

37h

“Resume Well GPIO GPE Enable (RGGPE)—Offset 34h” on page 838

3Bh

“Resume Well GPIO SMI Enable (RGSMI)—Offset 38h” on page 839

3Fh

“Resume Well GPIO Trigger Status (RGTS)—Offset 3Ch” on page 839

43h

“Core Well GPIO NMI Enable (CGNMIEN)—Offset 40h” on page 840

47h

“Resume Well GPIO NMI Enable (RGNMIEN)—Offset 44h” on page 840

Default

Value

00000000h

00000000h

00000000h

00000000h

00000000h

00000000h

21.6.5.1

Core Well GPIO Enable (CGEN)—Offset 0h

Access Method

Type: I/O Register

(Size: 32 bits)

CGEN: [GBA] + 0h

GBA Type: PCI Configuration Register (Size: 32 bits)

GBA Reference: [B:0, D:31, F:0] + 44h

Default: 00000003h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000011

Bit

Default &

Range Access

Description

31:2

0b

RO

Reserved (RSV): Reserved.

1:0

11b

RW

Enable (EN): When set, enables the pin as a GPIO.

21.6.5.2

Core Well GPIO Input/Output Select (CGIO)—Offset 4h

Access Method

Type: I/O Register

(Size: 32 bits)

CGIO: [GBA] + 4h

GBA Type: PCI Configuration Register (Size: 32 bits)

GBA Reference: [B:0, D:31, F:0] + 44h

Default: 00000003h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000011

Bit

Default &

Range Access

Description

31:2

0b

RO

Reserved (RSV): Reserved.

1:0

11b

RW

Input/output (IO): When set, the GPIO signal (if enabled) is programmed as an

input. When cleared, the GPIO signal is programmed as an output.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

833

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