DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Table 120. Summary of Memory Mapped I/O Registers—RCBA
Offset
Start
3020h
3022h
3024h
3028h
302Ch
3030h
3034h
3038h
303Ch
3040h
3044h
3048h
304Ch
3050h
3054h
3058h
305Ch
3060h
3064h
3070h
3074h
3076h
3078h
307Ch
3080h
3084h
3088h
Offset End
Register ID—Description
Default
Value
3021h
3023h
3027h
302Bh
302Fh
3033h
3037h
303Bh
303Fh
3043h
3047h
304Bh
304Fh
3053h
3057h
305Bh
305Fh
3063h
3067h
3073h
3075h
3077h
307Bh
307Fh
3083h
3087h
308Bh
“SPI Status (SPISTS)—Offset 3020h†on page 843
0001h
“SPI Control (SPICTL)—Offset 3022h†on page 844
4001h
“SPI Address (SPIADDR)—Offset 3024h†on page 845
00000000h
“SPI Data 0 - Lower 32 Bits (SPID0_1)—Offset 3028h†on page 846
00000000h
“SPI Data 0 - Upper 32 Bits (SPID0_2)—Offset 302Ch†on page 846
00000000h
“SPI Data 1 - Lower 32 Bits (SPID1_1)—Offset 3030h†on page 846
00000000h
“SPI Data 1 - Upper 32 Bits (SPID1_2)—Offset 3034h†on page 847
00000000h
“SPI Data 2 - Lower 32 Bits (SPID2_1)—Offset 3038h†on page 847
00000000h
“SPI Data 2 - Upper 32 Bits (SPID2_2)—Offset 303Ch†on page 847
00000000h
“SPI Data 3 - Lower 32 Bits (SPID3_1)—Offset 3040h†on page 848
00000000h
“SPI Data 3 - Upper 32 Bits (SPID3_2)—Offset 3044h†on page 848
00000000h
“SPI Data 4 - Lower 32 Bits (SPID4_1)—Offset 3048h†on page 848
00000000h
“SPI Data 4 - Upper 32 Bits (SPID4_2)—Offset 304Ch†on page 849
00000000h
“SPI Data 5 - Lower 32 Bits (SPID5_1)—Offset 3050h†on page 849
00000000h
“SPI Data 5 - Upper 32 Bits (SPID5_2)—Offset 3054h†on page 850
00000000h
“SPI Data 6 - Lower 32 Bits (SPID6_1)—Offset 3058h†on page 850
00000000h
“SPI Data 6 - Upper 32 Bits (SPID6_2)—Offset 305Ch†on page 850
00000000h
“SPI Data 7 - Lower 32 Bits (SPID7_1)—Offset 3060h†on page 851
00000000h
“SPI Data 7 - Upper 32 Bits (SPID7_2)—Offset 3064h†on page 851
00000000h
“BIOS Base Address (BBAR)—Offset 3070h†on page 851
00000000h
“Prefix Opcode Configuration (PREOP)—Offset 3074h†on page 852
0004h
“Opcode Type Configuration (OPTYPE)—Offset 3076h†on page 853
0000h
“Opcode Menu Configuration - Lower 32 Bits (OPMENU_1)—Offset 3078h†on page 853 00000005h
“Opcode Menu Configuration - Upper 32 Bits (OPMENU_2)—Offset 307Ch†on page 854 00000000h
“Protected BIOS Range 0 (PBR0)—Offset 3080h†on page 855
00000000h
“Protected BIOS Range 1 (PBR1)—Offset 3084h†on page 855
00000000h
“Protected BIOS Range 2 (PBR2)—Offset 3088h†on page 856
00000000h
21.7.4.1 SPI Status (SPISTS)—Offset 3020h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
SPISTS: [RCBA] + 3020h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 0001h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
843
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