DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
7
0b
RO
Reserved (RSV): Reserved.
6:4
0b
RW
Cycle Opcode Pointer (COPTR): This field selects one of the programmed opcodes in
the Opcode Menu Configuration register to be used as the SPI Command/Opcode. In the
case of an Atomic Cycle Sequence, this determines the second command.
Sequence Prefix Opcode Pointer (SOPTR): This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A
3
0b
RW
value of 0 points to the opcode in the least significant byte of the Prefix Opcode
Configuration register. By making this programmable, the processor supports flash
devices that have different opcodes for enabling writes to the data space vs. status
register.
Atomic Cycle Sequence (ACS): When set to 1 along with the SCGO assertion, the
processor will execute a sequence of commands on the SPI interface without allowing
the other SPI master component to arbitrate and interleave cycles. The sequence is
2
0b
RW
composed of: Atomic Sequence Prefix Command (8-bit opcode only) Primary Command
specified by software (can include address and data) Polling the Flash Status Register
(opcode 05h) until bit 0 becomes 0b. The SPI Cycle in Progress bit remains set and the
Cycle Done Status bit in the SPI Status register remains unset until the Busy bit in the
Flash Status Register returns 0.
Cycle Go (CG): This bit always returns 0 on reads. However, a write to this register
with a 1 in this bit starts the SPI cycle defined by the other bits of this register. The SPI
1
0b
RW/S
Cycle in Progress (SCIP) bit in the SPI Status register gets set by this action. Hardware
must ignore writes to this bit while the SPI Cycle In Progress bit is set. Hardware allows
other bits in this register to be programmed for the same transaction when writing this
bit to 1. This saves an additional memory write.
0
1b
RW
Access Request (AR): This bit is used by the software to request that the other SPI
master stop initiating long transactions on the SPI bus. This bit defaults to a 1 and must
be cleared by BIOS after completing the accesses for the boot process.
21.7.4.3
SPI Address (SPIADDR)—Offset 3024h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
SPIADDR: [RCBA] + 3024h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
CSC: Chip Select Control: These two bits control which SPI Chip Select is used. Default
00 must always select SS0. Direct read mode always uses SS0.
31:30
0b
RW
00 : SS0
01 : SS1
10 : SS2
11 : SS3
29:24
0b
RO
Reserved (RSV): Reserved.
23:0
0b
RW
Cycle Address (CA): This field is shifted out as the SPI Address (MSB first).
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
845
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