DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Figure 47. Legacy SPI Register Map

PCI Space

CPU

Core

PCI

CAM

(I/O)

PCI

ECAM

(Mem)

Bus 0

SPI0 F:0

SPI1 F:1

I2C*/GPIO F:2

SDIO/eMMC F:0

HSUART0 F:1

USB Device F:2

EHCI Host F:3

OCHI Host F:4

HSUART1 F:5

MAC0 F:6

MAC1 F:7

Host Bridge

D:0,F:0

RP0 F:0

RP0 F:1

Legacy PCI

Header

D:31,F:0

RCBA_BAR

Legacy Bridge

D:31,F:0

Memory

Space

SPI Host

Interface

Registers

I/O Space

21.7.4

Warning:

§§

Legacy SPI Host Interface Registers

The SPI Host Interface registers are memory-mapped in the RCRB Memory Space in

offset range 3020h to 308Fh.

Address locations that are not listed are considered reserved register locations. Reads

to reserved registers may return non-zero values. Writes to reserved locations may

cause system failure.

Intel® Quark SoC X1000

DS

842

October 2013

Document Number: 329676-001US

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