DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

Bit

Default &

Range Access

Description

31:0

0b

RW

Cycle Data (CD): This field is shifted out during the data portion of the SPI cycle. This

register also shifts in the data during the data portion of the SPI cycle

21.7.4.18 SPI Data 7 - Lower 32 Bits (SPID7_1)—Offset 3060h

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

SPID7_1: [RCBA] + 3060h

RCBA Type: PCI Configuration Register (Size: 32 bits)

RCBA Reference: [B:0, D:31, F:0] + F0h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:0

0b

RW

Cycle Data (CD): This field is shifted out during the data portion of the SPI cycle. This

register also shifts in the data during the data portion of the SPI cycle

21.7.4.19 SPI Data 7 - Upper 32 Bits (SPID7_2)—Offset 3064h

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

SPID7_2: [RCBA] + 3064h

RCBA Type: PCI Configuration Register (Size: 32 bits)

RCBA Reference: [B:0, D:31, F:0] + F0h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:0

0b

RW

Cycle Data (CD): This field is shifted out during the data portion of the SPI cycle. This

register also shifts in the data during the data portion of the SPI cycle

21.7.4.20 BIOS Base Address (BBAR)—Offset 3070h

This register is not writable when the SPI Configuration Lock-Down bit in the SPI Status

register is set.

Access Method

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

851

Share Link: