DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

The Control Word Register at port 43h controls the operation of all three counters.

Several commands are available:

• Control Word Command: Specifies which counter to read or write, the operating

mode, and the count format (binary or BCD).

• Counter Latch Command: Latches the current count so that it can be read by the

system. The countdown process continues.

• Read Back Command: Reads the count value, programmed mode, the current

state of the OUT pins, and the state of the Null Count Flag of the selected counter.

Table 121 lists the six operating modes for the interval counters.

Table 121. Counter Operating Modes

Mode

0

1

2

3

4

5

Function

Description

Out signal on end of count (=0)

Output is 0. When count goes to 0, output goes to 1 and

stays at 1 until counter is reprogrammed.

Hardware retriggerable one-shot

Output is 0. When count goes to 0, output goes to 1 for one

clock time.

Rate generator (divide by n counter)

Output is 1. Output goes to 0 for one clock time, then back to

1 and counter is reloaded.

Square wave output

Output is 1. Output goes to 0 when counter rolls over, and

counter is reloaded. Output goes to 1 when counter rolls

over, and counter is reloaded, etc.

Software triggered strobe

Output is 1. Output goes to 0 when count expires for one

clock time.

Hardware triggered strobe

Output is 1. Output goes to 0 when count expires for one

clock time.

21.8.2.2 Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in

progress. There are three methods for reading the counters: a simple read operation,

counter Latch Command, and the Read-Back Command. Each is explained below.

With the simple read and counter latch command methods, the count must be read

according to the programmed format; specifically, if the counter is programmed for two

byte counts, two bytes must be read. The two bytes do not have to be read one right

after the other. Read, write, or programming operations for other counters may be

inserted between them.

21.8.2.2.1

Simple Read

The first method is to perform a simple read operation. The counter is selected through

port 40h (counter 0), 41h (counter 1), or 42h (counter 2).

Note:

Performing a direct read from the counter does not return a determinate value,

because the counting process is asynchronous to read operations. However, in the case

of counter 2, the count can be stopped by writing to the NSC.CNTR2_ENABLE register

field.

21.8.2.2.2 Counter Latch Command

The Counter Latch Command, written to port 43h, latches the count of a specific

counter at the time the command is received. This command is used to ensure that the

count read from the counter is accurate, particularly when reading a two-byte count.

The count value is then read from each counter's Count Register as was programmed

by the Control Register.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

859

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