DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
31:24
23:16
15:8
7:0
0b
RW/L
0b
RW/L
0b
RW/L
0h
RW/L
Allowable Opcode 7 (AO7): See the description for bits 7:0
Allowable Opcode 6 (AO6): See the description for bits 7:0
Allowable Opcode 5 (AO5): See the description for bits 7:0
Allowable Opcode 4 (AO4): Software programs an SPI opcode into this field for use
when initiating SPI commands through the Control Register.
21.7.4.25 Protected BIOS Range 0 (PBR0)—Offset 3080h
This register cannot be written when the SPI Configuration Lock-Down bit in the SPI
Status register is set to 1.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
PBR0: [RCBA] + 3080h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31
30:24
23:12
11:0
0b
RW/L
0b
RO
0b
RW/L
0b
RW/L
Write Protection Enable (WPE): When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes directed to addresses between them
(inclusive) must be blocked by hardware. The base and limit fields are ignored when this
bit is cleared.
Reserved (RSV): Reserved.
Protected Range Limit (PRL): This field corresponds to SPI address bits 23:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Protected Range Base (PRB): This field corresponds to SPI address bits 23:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
000h for the base comparison. Any address less than the value programmed in this field
is unaffected by this protected range.
21.7.4.26 Protected BIOS Range 1 (PBR1)—Offset 3084h
This register cannot be written when the SPI Configuration Lock-Down bit in the SPI
Status register is set to 1.
Access Method
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
855
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