DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Type: Memory Mapped I/O Register
(Size: 32 bits)
BBAR: [RCBA] + 3070h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:24
23:8
7:0
0b
RO
0b
RW/L
0b
RO
Reserved (RSV2): Reserved.
Bottom of System Flash (BOSF): This field determines the bottom of the System
BIOS. The processor will not run Programmed commands nor memory reads whose
address field is less than this value. This field corresponds to bits 23:8 of the 3-byte
address; bits 7:0 are assumed to be 00h for this vector when comparing to a potential
SPI address. Software must always program 1s into the upper, Don't Care bits of this
field based on the flash size. Hardware does not know the size of the flash array and
relies upon the correct programming by software. The default value of 0000h results in
all cycles allowed.
Note: The SPI Host Controller prevents any Programmed cycle using the Address
Register with an address less than the value in this register. Some flash devices specify
that the Read ID command must have an address of 0000h or 0001h. If this command
must be supported with these devices, it must be performed with the BBAR - BIOS Base
Address programmed to 0h. Some of these devices have actually been observed to
ignore the upper address bits of the Read ID command.
Reserved (RSV1): Reserved.
21.7.4.21 Prefix Opcode Configuration (PREOP)—Offset 3074h
This register is not writable when the SPI Configuration Lock-Down bit in the SPI Status
register is set.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PREOP: [RCBA] + 3074h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 0004h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Bit
Default &
Range Access
Description
15:8
7:0
0h
RW/L
04h
RW/L
Prefix Opcode 1 (PO1): Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
Prefix Opcode 2 (PO2): Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
Intel® Quark SoC X1000
DS
852
October 2013
Document Number: 329676-001US
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