DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

Figure 48. 8254 Timers Register Map

PCI Space

CPU

Core

PCI

CAM

(I/O)

PCI

ECAM

(Mem)

Bus 0

SPI0 F:0

SPI1 F:1

I2C*/GPIO F:2

SDIO/eMMC F:0

HSUART0 F:1

USB Device F:2

EHCI Host F:3

OCHI Host F:4

HSUART1 F:5

MAC0 F:6

MAC1 F:7

Host Bridge

D:0,F:0

RP0 F:0

RP0 F:1

Legacy PCI

Header

D:31,F:0

Legacy Bridge

D:31,F:0

Memory

Space

IO Space

Fixed IO

Registers

21.8.4

Timer I/O Registers

The I/O ports listed in Table 122 have multiple register functions depending on the

current programmed state of the 8254. The port numbers referenced in the register

descriptions following Table 122 is one possible combination but not the only one.

Table 122. Register Aliases

Port Alias

Register Name

Counter 0 Interval Time Status Byte Format (C0TS)

40h 50h

Counter 0 Counter Access Port Register (C0AP)

Counter 1 Interval Time Status Byte Format (C1TS)

41h 51h

Counter 1 Counter Access Port Register (C1AP)

Default Value Access

0xxxxxxxb

RO

Undefined

RW

0xxxxxxxb

RO

Undefined

RW

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

861

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