DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Bit
Default &
Range Access
Description
7:0
01h
RO
Revision ID (RID): Indicates that revision 1.0 of the specification is implemented.
21.9.3.2
General Capabilities and ID Register - Upper 32 Bits (GCID_2)—Offset
4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
GCID_2: [0xFED00000] + 4h
Default: 0429B17Fh
31
28
24
20
16
12
8
4
0
00000100001010011011000101111111
Bit
Default &
Range Access
Description
31:0
0429B17Fh
RO
Counter
Tick
Period
(CTP):
Indicates
a
period
of
69.841279ns,
14.1318
MHz
clock.
21.9.3.3
General Configuration (GC)—Offset 10h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
GC: [0xFED00000] + 10h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:2
0b
RO
Reserved (RSV): Reserved.
Legacy Route Enable (LRE): When set, interrupts will be routed as follows: Timer 0
1
0b
RW
will be routed to IRQ0 in 8259 and IRQ2 in the I/O APIC Timer 1 will be routed to IRQ8
in 8259 and I/O APIC Timer 2 is routed to IRQ11 in 8259 and Timer 2 will be routed to
IOxAPIC as per the routing in T2C.IR When set, the TnC.IR will have no impact for
Timers 0 and 1.
Overall Enable (EN): When set, the timers can generate interrupts. When cleared, the
0
0b
RW
main counter will halt and no interrupts will be caused by any timer. For level-triggered
interrupts, if an interrupt is pending when this bit is cleared, the GIS.Tx will not be
cleared.
21.9.3.4
General Interrupt Status Register (GIS)—Offset 20h
Access Method
Intel® Quark SoC X1000
DS
870
October 2013
Document Number: 329676-001US
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