DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Figure 49. HPET Register Map

PCI Space

CPU

Core

PCI

CAM

(I/O)

PCI

ECAM

(Mem)

Bus 0

SPI0 F:0

SPI1 F:1

I2C*/GPIO F:2

SDIO/eMMC F:0

HSUART0 F:1

USB Device F:2

EHCI Host F:3

OCHI Host F:4

HSUART1 F:5

MAC0 F:6

MAC1 F:7

Host Bridge

D:0,F:0

RP0 F:0

RP0 F:1

Legacy PCI

Header

D:31,F:0

Legacy Bridge

D:31,F:0

Memory

Space

Fixed Mem

Registers

IO Space

21.9.3

Memory Mapped Registers

The HPET register space is memory mapped to a 1 KB block starting at address

FED00000h. All registers are in the core well and reset by RESET#. Accesses that cross

register boundaries result in undefined behavior.

Table 124. Summary of Memory Mapped I/O Registers—0xFED00000

Offset

Start

0h

4h

10h

Offset End

Register ID—Description

Default

Value

3h

“General Capabilities and ID Register - Lower 32 Bits (GCID_1)—Offset 0h” on page 869 8086A201h

7h

“General Capabilities and ID Register - Upper 32 Bits (GCID_2)—Offset 4h” on page 870 0429B17Fh

13h

“General Capabilities and ID Register - Lower 32 Bits (GCID_1)—Offset 0h” on page 869 00000000h

Intel® Quark SoC X1000

DS

868

October 2013

Document Number: 329676-001US

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