DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Legacy Bridge—Intel® Quark SoC X1000
7
4
0
0
X
X
X
X
X
X
X
21.8.4.3
Bit
Default &
Range Access
Description
7
6
5: 4
3: 1
0
0b
Counter State (CS): When set, OUT of the counter is set. When cleared, OUT of the
RO
counter is 0.
X
RO
Count Register (CR): When cleared, indicates when the last count written to the
Count Register (CR) has been loaded into the counting element (CE) and is available for
reading. The time this happens depends on the counter mode.
Read/Write Selection (RWS): These reflect the read/write selection made through
bits[5:4] of the control register. The binary codes returned during the status read match
X
RO
the codes used to program the counter read/write selection.
00 Counter Latch Command
01 Read/Write Least Significant Byte (LSB)
10 Read/Write Most Significant Byte (MSB)
11 Read/Write LSB then MSB
Mode (MD): Returns the counter mode programming. The binary code returned
matches the code used to program the counter mode, as listed under the bit function
above.
Bits Mode Description
X
000 0 Out signal on end of count (=0)
RO
001 1 Hardware retriggerable one-shot
x10 2 Rate generator (divide by n counter)
x11 3 Square wave output
100 4 Software triggered strobe
101 5 Hardware triggered strobe
X
Countdown Type (CT): 0 for binary countdown or a 1 for binary coded decimal (BCD)
RO
countdown.
Counter 2 Interval Time Status Byte Format (C2TS)—Offset 42h
Access Method
Type: I/O Register
(Size: 8 bits)
C2TS: 42h
7
4
0
0
X
X
X
X
X
X
X
Bit
Default &
Range Access
Description
7
6
5: 4
0b
Counter State (CS): When set, OUT of the counter is set. When cleared, OUT of the
RO
counter is 0.
X
RO
Count Register (CR): When cleared, indicates when the last count written to the
Count Register (CR) has been loaded into the counting element (CE) and is available for
reading. The time this happens depends on the counter mode.
Read/Write Select ion (RWS): These reflect the read/write selection made through
bits[5:4] of the control register. The binary codes returned during the status read match
X
RO
the codes used to program the counter read/write selection.
00 Counter Latch Command
01 Read/Write Least Significant Byte (LSB)
10 Read/Write Most Significant Byte (MSB)
11 Read/Write LSB then MSB
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
863
Share Link: 