DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

Table 124. Summary of Memory Mapped I/O Registers—0xFED00000 (Continued)

Offset

Start

20h

F0h

F4h

100h

104h

108h

10Ch

120h

124h

128h

140h

144h

148h

Offset End

Register ID—Description

23h

F3h

F7h

103h

107h

10Bh

10Fh

123h

127h

12Bh

143h

147h

14Bh

“General Interrupt Status Register (GIS)—Offset 20h” on page 870

“Main Counter Value Register - Lower 32 Bits (MCV_1)—Offset F0h” on page 871

“Main Counter Value Register - Upper 32 Bits (MCV_2)—Offset F4h” on page 871

“Timer 0 Config and Capabilities Register - Lower 32 Bits (T0C_1)—Offset 100h” on

page 872

“Timer 0 Config and Capabilities Register - Upper 32 Bits (T0C_2)—Offset 104h” on

page 873

“Timer 0 Comparator Value Register - Lower 32 Bits (T0CV_1)—Offset 108h” on

page 873

“Timer 0 Comparator Value Register - Upper 32 Bits (T0CV_2)—Offset 10Ch” on

page 873

“Timer 1 Config and Capabilities Register - Lower 32 Bits (T1C_1)—Offset 120h” on

page 874

“Timer 1 Config and Capabilities Register - Upper 32 Bits (T1C_2)—Offset 124h” on

page 875

“Timer 1 Comparator Value Register (T1CV_1)—Offset 128h” on page 875

“Timer 2 Config and Capabilities Register - Lower 32 Bits (T2C_1)—Offset 140h” on

page 875

“Timer 2 Config and Capabilities Register - Upper 32 Bits (T2C_2)—Offset 144h” on

page 876

“Timer 2 Comparator Value Register (T2CV_1)—Offset 148h” on page 877

Default

Value

00000000h

00000000h

00000000h

00000030h

00F00000h

FFFFFFFFh

FFFFFFFFh

00000000h

00F00000h

FFFFFFFFh

00000000h

00F00800h

FFFFFFFFh

21.9.3.1

General Capabilities and ID Register - Lower 32 Bits (GCID_1)—Offset

0h

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

GCID_1: [0xFED00000] + 0h

Default: 8086A201h

31

28

24

20

16

12

8

4

0

10000000100001101010001000000001

Bit

Default &

Range Access

Description

31:16

15

14

13

12:8

8086h

RO

1b

RO

0b

RO

1b

RO

00010b

RO

Vendor ID (VID): Value of 8086h indicates Intel.

Legacy Route Capable (LRC): Indicates support for Legacy Interrupt Route.

Reserved (RSV): Reserved.

Counter Size (CS): This bit is set to indicate that the main counter is 64 bits wide.

Number of Timers (NT): Indicates that 3 timers are supported.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

869

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