DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

21.9.1.3

Interrupts

If each timer has a unique interrupt and the timer has been configured for edge-

triggered mode, then there are no specific steps required. If configured to level-

triggered mode, then its interrupt must be cleared by software by writing a '1' back to

the bit position for the interrupt to be cleared.

Interrupts associated with the various timers have several interrupt mapping options.

Software should mask GCFG.LRE when reprogramming HPET interrupt routing to avoid

spurious interrupts.

21.9.1.3.1

Mapping Option #1: Legacy Option (GCFG.LRE set)

This forces the following mapping:

Table 123. 8254 Interrupt Mapping

Timer 8259 Mapping APIC Mapping

Comment

0

IRQ0

1

IRQ8

2

T2C.IR

IRQ2

IRQ8

T2C.IRC

The 8254 timer does not cause any interrupts

RTC does not cause any interrupts.

21.9.1.3.2 Mapping Option #2: Standard Option (GCFG.LRE cleared)

Each timer has its own routing control. The interrupts can be routed to various

interrupts in the I/O APIC. T[2:0]C.IRC indicates which interrupts are valid options for

routing. If a timer is set for edge-triggered mode, the timers should not be shared with

any other interrupts.

21.9.2

Register Map

See Chapter 5.0, “Register Access Methods” for additional information.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

867

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