DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

21.8.4.4

Bit

Default &

Range Access

Description

3: 1

0

Mode (MD): Returns the counter mode programming. The binary code returned

matches the code used to program the counter mode, as listed under the bit function

above.

Bits Mode Description

X

000 0 Out signal on end of count (=0)

RO

001 1 Hardware retriggerable one-shot

x10 2 Rate generator (divide by n counter)

x11 3 Square wave output

100 4 Software triggered strobe

101 5 Hardware triggered strobe

X

Countdown Type (CT): 0 for binary countdown or a 1 for binary coded decimal (BCD)

RO

countdown.

Timer Control Word Register (TCW)—Offset 43h

Access Method

Type: I/O Register

(Size: 8 bits)

TCW: 43h

7

4

0

X

X

X

X

X

X

X

X

21.8.4.5

Bit

Default &

Range Access

Description

7: 6

5: 4

3: 1

0

Counter Select (CS): The Counter Selection bits select the counter the control word

acts upon as shown below. The Read Back Command is selected when bits[7:6] are both

X

WO

1.

00 Counter 0 select

01 Counter 1 select

10 Counter 2 select

11 Read Back Command

Read/Write Select (RWS): The counter programming is done through the counter

port (40h for counter 0, 41h for counter 1, and 42h for counter 2)

X

00 Counter Latch Command

WO 01 Read/Write Least Significant Byte (LSB)

10 Read/Write Most Significant Byte (MSB)

11 Read/Write LSB then MSB

Counter Mode Selection (CMS): Selects one of six modes of operation for the

selected counter.

000 = Out signal on end of count (=0)

X

001 = Hardware retriggerable one-shot

WO x10 = Rate generator (divide by n counter)

x11 = Square wave output

100 = Software triggered strobe

101 = Hardware triggered strobe

X

Binary/BCD Countdown Select (BCS):

WO

0 = Binary countdown is used. The largest possible binary count is 216

1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104

Counter 0 Counter Access Port Register (C0AP)—Offset 50h

Access Method

Type: I/O Register

(Size: 8 bits)

C0AP: 50h

Intel® Quark SoC X1000

DS

864

October 2013

Document Number: 329676-001US

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