DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

21.9.1

21.9.1.1

21.9.1.2

Features

Non-Periodic Mode - All Timers

This mode can be thought of as creating a one-shot. When a timer is set up for non-

periodic mode, it generates an interrupt when the value in the main counter matches

the value in the timer's comparator register. As timers 1 and 2 are 32-bit, they

generate another interrupt when the main counter wraps.

T0CV cannot be programmed reliably by a single 64-bit write in a 32-bit environment

unless only the periodic rate is being changed. If T0CV must be re-initialized, the

following algorithm is performed:

1. Set T0C.TVS

2. Set T0CV[31:0]

3. Set T0C.TVS

4. Set T0CV[63:32]

Every timer is required to support the non-periodic mode of operation.

Periodic Mode - Timer 0 Only

In periodic mode, when the main counter value matches the value in T0CV, an interrupt

is generated (if enabled). Hardware then increases T0CV by the last value written to

T0CV. During run-time, T0CV can be read to find out when the next periodic interrupt

will be generated. Software is expected to remember the last value written to T0CV.

Example: if the value written to T0CV is 00000123h, then:

• An interrupt will be generated when the main counter reaches 00000123h.

• T0CV will then be adjusted to 00000246h.

• Another interrupt will be generated when the main counter reaches 00000246h.

• T0CV will then be adjusted to 00000369h.

When the incremented value is greater than the maximum value possible for T0CV, the

value wraps around through 0. For example, if the current value in a 32-bit timer is

FFFF0000h and the last value written to this register is 20000, then after the next

interrupt the value changes to 00010000h.

If software wants to change the periodic rate, it writes a new value to T0CV. When the

timer's comparator matches, the new value is added to derive the next matching point.

If software resets the main counter, the value in the comparator's value register must

also be reset by setting T0C.TVS. To avoid race conditions, this should be done with the

main counter halted. The following usage model is expected:

1. Software clears GCFG.EN to prevent any interrupts.

2. Software clears the main counter by writing a value of 00h to it.

3. Software sets T0C.TVS.

4. Software writes the new value in T0CV.

5. Software sets GCFG.EN to enable interrupts.

Intel® Quark SoC X1000

DS

866

October 2013

Document Number: 329676-001US

Share Link: