DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Enable opcodes in this menu. Malicious software could then perform writes and erases

to the SPI flash without using the atomic cycle mechanism. Write Enable opcodes

should only be programmed in the Prefix Opcode Configuration register.

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

OPMENU_1: [RCBA] + 3078h

RCBA Type: PCI Configuration Register (Size: 32 bits)

RCBA Reference: [B:0, D:31, F:0] + F0h

Default: 00000005h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000101

Bit

Default &

Range Access

Description

31:24

23:16

15:8

7:0

0b

RW/L

0b

RW/L

0b

RW/L

05h

RW/L

Allowable Opcode 3 (AO3): See the description for bits 7:0

Allowable Opcode 2 (AO2): See the description for bits 7:0

Allowable Opcode 1 (AO1): See the description for bits 7:0

Allowable Opcode 0 (AO0): Software programs an SPI opcode into this field for use

when initiating SPI commands through the Control Register.

21.7.4.24 Opcode Menu Configuration - Upper 32 Bits (OPMENU_2)—Offset

307Ch

This register is not writable when the SPI Configuration Lock-Down bit in the SPI Status

register is set. Eight entries are available in this register to give BIOS a sufficient set of

commands for communicating with the flash device, while also restricting what

malicious software can do. This keeps the hardware flexible enough to operate with a

wide variety of SPI devices. It is recommended that BIOS avoid programming Write

Enable opcodes in this menu. Malicious software could then perform writes and erases

to the SPI flash without using the atomic cycle mechanism. Write Enable opcodes

should only be programmed in the Prefix Opcode Configuration register.

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

OPMENU_2: [RCBA] + 307Ch

RCBA Type: PCI Configuration Register (Size: 32 bits)

RCBA Reference: [B:0, D:31, F:0] + F0h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Intel® Quark SoC X1000

DS

854

October 2013

Document Number: 329676-001US

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