DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Register Access Methods

Table 42.

5.4

Table 43.

5.5

Table 44.

Referenced I/O Register Access Method Example (PM1S Register)

Type: I/O Register

(Size: 16 bits)

PM1S: [PM1BLK] + 0h

PM1BLK Type: PCI Configuration Register (Size: 32 bits)

PM1BLK Reference: [B:0, D:31, F:0] + 48h

Memory Referenced Register Access

The SoC uses programmable base address registers (BARs) to set a range of physical

address (memory) locations that it uses to decode memory reads and writes from the

CPU to directly access a register. These BARs act as pointers to blocks of actual

memory mapped I/O (MMIO) registers. To access a memory referenced register for a

specific base address, start with that base address and add the register’s offset.

Example pseudocode for a read is shown below:

Register_Snapshot = MEMREAD([Mem_BAR]+Register_Offset)

Base address registers are often located in the PCI configuration space and are

programmable by the BIOS/OS. Other common base address register types include

fixed memory registers and I/O registers that point to MMIO register blocks.

Memory Mapped Register Access Method Example (ESD Register)

Type: Memory Mapped I/O Register

(Size: 32 bits)

ESD: [RCBA] + 4h

RCBA Type: PCI Configuration Register (Size: 32 bits)

RCBA Reference: [B:0, D:31, F:0] + F0h

PCI Configuration Register Access

Access to PCI configuration space registers is performed through one of two different

configuration access methods (CAMs):

• I/O indexed - PCI CAM

• Memory mapped - PCI Enhanced CAM (ECAM)

Each PCI function (see Section 6.3, “PCI Configuration Space” on page 95) has a

standard PCI header consisting of 256 bytes for the I/O access scheme (CAM), or 4096

bytes for the enhanced memory access method (ECAM). Invalid read accesses return

binary strings of 1s.

PCI Register Access Method Example (PCI_DEVICE_VENDOR Register)

Type: PCI Configuration Register

(Size: 32 bits)

PCI_DEVICE_VENDOR: [B:0, D:31, F:0] + 0h

5.5.1

PCI Configuration Access - CAM: I/O Indexed Scheme

Accesses to configuration space using the I/O method rely on two 32-bit I/O registers:

• CONFIG_ADDRESS - I/O Port CF8h

• CONFIG_DATA - I/O Port CFCh

These two registers are both 32-bit registers in I/O space. Using this indirect access

mode, software uses CONFIG_ADDRESS (CF8h) as an index register, indicating which

configuration space register to access, and CONFIG_DATA (CFCh) acts as a window to

Intel® Quark SoC X1000

DS

84

October 2013

Document Number: 329676-001US

Share Link: