DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Mapping Address Spaces—Intel® Quark SoC X1000

6.0

Note:

6.1

6.1.1

Mapping Address Spaces

The Intel® Quark SoC X1000 supports four different address spaces:

• Physical Address Space (Memory Space)

• I/O Space

• PCI Configuration Space

• Message Bus Space

The CPU core can only directly access memory space through memory reads and writes

and I/O space through the IN and OUT I/O port instructions. PCI configuration space is

indirectly accessed through I/O or memory space, and the Message Bus space is

accessed through PCI configuration space. See Chapter 5.0, “Register Access Methods”

for details.

This chapter describes how the memory, I/O, PCI, and Message Bus spaces are mapped

to interfaces in the SoC.

See Chapter 12.0, “Host Bridge” for registers specified in the chapter.

Physical Address Space Mappings

There are 4 Gbyte (32-bits) of physical address space that can be used as:

• Memory Mapped I/O (MMIO - I/O fabric)

• Physical Memory (DRAM)

The CPU core can access the full physical address space, while downstream devices can

only access SoC DRAM, and the CPU core’s local APIC. Peer to peer transactions are not

supported.

Most devices map their registers and memory to the physical address space. This

chapter summarizes the possible mappings.

Bridge Memory Map

The Host Bridge maps the physical address space as follows:

• CPU core to DRAM

• CPU core to I/O fabric (MMIO)

• CPU core to extended PCI registers (ECAM accesses)

• I/O fabric to CPU cores (local APIC interrupts)

This SoC has the following distinct memory regions:

• DOS DRAM + Low DRAM

• MMIO

The HMBOUND register is used to create these memory regions, as shown in Figure 12.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

89

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