DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Register Access Methods

5.6

Table 47.

Message Bus Register Access

Accesses to the message bus space are through the Host Bridge’s PCI configuration

registers. This unit relies on three 32-bit PCI configuration registers to generate

messages:

• Message Bus Control Register (MCR) - PCI[B:0,D:0,F:0] + D0h

• Message Data Register (MDR) - PCI[B:0,D:0,F:0] + D4h

• Message Control Register eXtension (MCRX) - PCI[B:0,D:0,F:0] + D8h

This indirect access mode is similar to PCI CAM. Software uses the MCR/MCRX as an

index register, indicating which message bus space register to access (MCRX only when

required), and MDR as the data register. Writes to the MCR trigger message bus

transactions.

Writes to MCRX and MDR are captured. Writes to MCR generates an internal ‘message

bus’ transaction with the opcode and target (port, offset, byte enable) specified in the

MCR and the captured MCRX. When a write opcode is specified in MCR, the data that

was captured by MDR is used for the write. When a data read opcode is specified in

MCR, the data is available in the MDR register after the MCR write completes (non-

posted). The format of MCR and MCRX are shown in Table 47 and Table 48.

MCR Description

Field

OpCode (typically 10h for read, 11h for write)

Port

Offset/Register

Byte Enable

MBPR Bits

31:24

23:16

15:08

07:04

Table 48.

MCRX Description

Field

Offset/Register Extension. This is used for messages sent to end points that require more

than 8 bits for the offset/register. These bits are a direct extension of MCR[15:8].

MBPER Bits

31:08

Most message bus registers are located in the Host Bridge. The default opcode

messages for those registers are as follows:

• Message ‘Read Register’ Opcode: 10h

• Message ‘Write Register’ Opcode: 11h

Registers with different opcodes are specified as applicable. Pseudocode of a message

bus register read is shown below (where ReadOp==0x10):

MyMCR[31:24] = ReadOp; MyMCR[23:16] = port; MyMCR[15:8] = offset;

MyMCR[7:4] = 0xf

PCIWRITE(0, 0, 0, 0xD0, MyMCR)

Register_Snapshot = PCIREAD(0, 0, 0, 0xD4)

Intel® Quark SoC X1000

DS

86

October 2013

Document Number: 329676-001US

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