DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Register Access Methods—Intel® Quark SoC X1000
5.7
Register Field Access Types
Table 49.
Register Access Types and Definitions
Access Type
RO
WO
R/W
R/WC
R/WO
R/WL
R/WLO
R/W/SN
Reserved
Default
Meaning
Description
Read Only
Write Only
Read/Write
Read/Write Clear
Read/Write-Once
Read/Write Lockable
Read/Write, Lock-
Once
Read/Write
Reserved
Default
In some cases, if a register is read only, writes to this register
location have no effect. However, in other cases, two separate
registers are located at the same location where a read accesses
one of the registers and a write accesses the other register. See the
I/O and memory map tables for details.
In some cases, if a register is write only, reads to this register
location have no effect. However, in other cases, two separate
registers are located at the same location where a read accesses
one of the registers and a write accesses the other register. See the
I/O and memory map tables for details.
A register with this attribute can be read and written.
A register bit with this attribute can be read and written. However, a
write of 1 clears (sets to 0) the corresponding bit and a write of 0
has no effect.
A register bit with this attribute can be written only once after power
up. After the first write, the bit becomes read only.
A register bit with the attribute can be read at any time but writes
may only occur if the associated lock bit is set to unlock. If the
associated lock bit is set to lock, this register bit becomes RO unless
otherwise indicated.
A register bit with this attribute can be written to the non-locked
value multiple times, but to the locked value only once. After the
locked value has been written, the bit becomes read only.
Read/Write register initial value loaded from NVM.
The value of reserved bits must never be changed.
When the processor is reset, it sets its registers to predetermined
default states. The default state represents the minimum
functionality feature set required to successfully bring up the
system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization
software to determine configuration, operating parameters, and
optional system features that are applicable, and to program the
processor registers accordingly.
§§
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
87
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