T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

Table 3. Recommended operating conditions

Characteristic

Symbol

Recommended Value Unit Notes

5. Selecting RGMII limits to LVDD = 2.5 V.

6. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage

levels.

7. Voltage ID (VID) operating range is between 0.975 to 1.025V. Regulator selection should be based on Vout range of at

least 0.9 to 1.1 V, with resolution of 12.5 mV or better.

8. Keep the filter close to the pin. Voltage and tolerance for AVDD is defined at the input of the PLL supply filter and not the

pin of AVDD.

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

Nominal C/D/S/G/L/OVDD + 20%

C/D/S/G/L/OVDD + 5%

VIH

C/D/S/G/L/OVDD

GND

GND - 0.3 V

VIL

GND - 0.7 V

Not to exceed 10% of tCLOCK1

Note:

tCLOCK refers to the clock period associated with the respective interface:

For I2C ODVDD, tCLOCK references SYSCLK.

For DDR GVDD, tCLOCK references Dn_MCLK.

For eSPI OCVDD, tCLOCK references SPI_CLK.

For JTAG OVDD, tCLOCK references TCK.

For SerDes SVDD, tCLOCK references SD_REF_CLK.

For Ethernet LVDD, tCLOCK references ECn_GTX_CLK125.

Figure 7. Overshoot/Undershoot voltage for CVDD/GVDD/LVDD/OVDD/SVDD/DVDD

The core and platform voltages must always be provided at nominal VID. See Table 3 for

actual recommended core voltage. Voltage to the processor interface I/Os are provided

through separate sets of supply pins and must be provided at the voltages shown in Table

3. The input voltage threshold scales with respect to the associated I/O supply voltage.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

47

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