T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
DVDD, OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy
appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential
receivers referenced by the externally supplied D1_MVREF signal (nominally set to
GVDD/2) as is appropriate for the SSTL_1.35/SSTL_1.5 electrical signaling standard.
The DDR DQS receivers cannot be operated in single-ended fashion. The complement
signal must be properly driven and cannot be grounded.
3.1.3 Output driver characteristics
This chip provides information on the characteristics of the output driver strengths.
NOTE
These values are preliminary estimates.
Table 4. Output drive capability
Driver type
Output impedance (Ω)
Supply Voltage Notes
Minimu
m2
Typical
Maxim
um3
DDR3 signal
—
18 (full-strength mode)
—
G1VDD = 1.5 V 1
27 (half-strength mode)
DDR3L signal
—
18 (full-strength mode)
—
G1VDD = 1.35 V 1
27 (half-strength mode)
Ethernet signals
45
—
90
L1VDD / LVDD = —
3.3 V
40
—
90
L1VDD / LVDD =
2.5 V
40
—
75
L1VDD / LVDD =
1.8 V
MPIC, GPIO, system control and power
23
—
management, clocking, debug, IFC, DDRCLK
supply, and JTAG I/O voltage
51
OVDD, O1VDD = —
1.8 V
DUART, DMA, MPIC, QE, TDM, I2C, DIU
45
—
40
—
40
—
eSPI, SDHC_WP, SDHC_CD
45
—
40
—
eSDHC
45
—
40
—
Notes:
90
DVDD = 3.3 V
—
90
DVDD = 2.5 V
75
DVDD = 1.8 V
90
CVDD = 3.3 V
—
75
CVDD = 1.8 V
90
EVDD = 3.3 V
—
75
EVDD = 1.8 V
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at G1VDD (min).
2. Estimated number based on best case processed device.
3. Estimated number based on worst case processed device.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
48
NXP Semiconductors
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