T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
From a system standpoint, if any of the I/O power
supplies ramp prior to the VDD supplies, there will be a
brief period as the VDD powers up that the I/Os
associated with that I/O supply may go from being tri-
stated to an indeterminate state (either driven to a logic
one or zero) and extra current may be drawn by the
device.
Only 300,000 POR cycles are permitted per lifetime of
a device. Note that this value is based on design
estimates and is preliminary.
If using Trust Architecture Security Monitor battery-backed features, prior to VDD
ramping up to the 0.5 V level, ensure that OVDD is ramped to the recommended
operational voltage and SYSCLK is running. The clock should have a minimum
frequency of 800 Hz and a maximum frequency no greater than the supported system
clock frequency for the device.
All supplies must be at their stable values within 400 ms.
This figure provides the PROG_SFP timing diagram.
Fuse programming
PROG_SFP
VDD
10% PROG_SFP
10% PROG_SFP
90t%PRVODGD _SFP_VDD
PORESET_B
90% OVDD
tPROG_SFP_PROG
tPROG_SFP_DELAY
90% OVDD
tPROG_SFP_RST
NOTE: PROG_SFP must be stable at 1.80 V prior to initiating fuse programming.
Figure 8. PROG_SFP timing diagram
This table provides information on the power-down and power-up sequence parameters
for PROG_SFP.
Table 5. PROG_SFP timing 5
Driver type
tPROG_SFP_DELAY
Min
100
Max
—
Table continues on the next page...
Unit
SYSCLKs
Notes
1
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
50
NXP Semiconductors
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