Electrical characteristics
3.2 Power sequencing
The chip requires that its power rails be applied in a specific sequence in order to ensure
proper device operation. For power up, these requirements are as follows:
1. Bring up VDD, SnVDD, USB_SVDD, VDD_LP, USB_HVDD, LVDD, DVDD, CVDD,
USB_OVDD, OVDD, TH_VDD, AVDD (cores, platform, DDR), G1VDD, XnVDD, and
AVDD_ SDn_PLLn. Drive PROG_SFP = GND.
• PORESET_B input must be driven asserted and held during this step.
Power supplies in step 1 have no ordering requirement with respect to one another
except for the USB power supplies per the following note.
NOTE
a. USB_SVDD supply must ramp before or after the
USB_HVDD and USB_OVDD supplies have ramped.
The supply set that ramp first must reach 90% of its
final value before a supply from the other set can be
ramped up.
b. USB_HVDD and USB_OVDD supplies among
themselves are sequence independent.
c. USB_HVDD rise time (10% to 90%) has a minimum of
100 us.
2. Negate PORESET_B input as long as the required assertion/hold time has been met
per Table 19.
3. For secure boot fuse programming, use the following steps:
a. After negation of PORESET_B, drive PROG_SFP = 1.80 V after a required
minimum delay per Table 5.
b. After fuse programming is completed, it is required to return PROG_SFP =
GND before the system is power cycled (PORESET_B assertion) or powered
down (VDD ramp down) per the required timing specified in Table 5. See
Security fuse processor, for additional details.
Warning
No activity other than that required for secure boot fuse
programming is permitted while PROG_SFP is driven
to any voltage above GND, including the reading of the
fuse block. The reading of the fuse block may only
occur while PROG_SFP = GND.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
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