Preliminary Technical Data
ADSP-BF512/BF514/BF516/BF518 (F)
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
Max
Unit
VDDINT Internal Supply Voltage1
VDDEXT2 External Supply Voltage3
VDDRTC4 RTC Power Supply Voltage
VDDMEM5 MEM Supply Voltage
VDDFLASH4 Internal SPI Flash Supply
Voltage
tbd
tbd
tbd
V
1.70
1.8, 2.5 or 3.3 3.6
V
2.25
3.6
V
1.70
1.8, 2.5 or 3.3 3.6
V
1.7
1.8
1.9
V
VDDOTP
VPPOTP
OTP Supply Voltage
OTP Programming Voltage
For Reads2
For Writes6
2.25
2.5
2.25
2.5
6.9
7.0
2.75
V
2.75
V
7.1
V
VIH
VIH
VIH
VIHTWI
VIL
VIL
VIL
VILTWI
TJ
TJ
TJ
High Level Input Voltage7, 8
High Level Input Voltage7, 8
High Level Input Voltage7, 8
High Level Input Voltage
Low Level Input Voltage7, 8
Low Level Input Voltage7, 8
Low Level Input Voltage7, 8
Low Level Input Voltage
Junction Temperature
Junction Temperature
Junction Temperature
VDDEXT/VDDMEM = 1.90 V
VDDEXT/VDDMEM = 2.75 V
VDDEXT/VDDMEM = 3.6 V
VDDEXT = 1.90 V/2.75 V/3.6 V
VDDEXT/VDDMEM = 1.7 V
VDDEXT/VDDMEM = 2.25 V
VDDEXT/VDDMEM = 3.0 V
VDDEXT = minimum
168-Ball CSP_BGA @ TAMBIENT = 0°C to + 70°C
176-Lead LQFP @ TAMBIENT = 0°C to + 70°C
176-Lead LQFP @ TAMBIENT = –40°C to + 85°C
1.1
1.7
2.0
0.7 x VBUSTWI
–0.3
–0.3
–0.3
–0.3
0
0
–40
3.6
V
3.6
V
3.6
V
VBUSTWI9
V
0.6
V
0.7
V
0.8
V
0.3 x VBUSTWI10 V
+105
°C
+105
°C
+105
°C
1 The expected nominal value is 1.4V ± 5% and initial customer designs should design with a programmable regulator that can be adjusted from 0.95V to 1.5V in 50mV steps.
2 Must remain powered (even if the associated function is not used).
3 VDDEXT is the supply to the GPIO.
4 If not used, power with VDDEXT.
5 Pins/balls that use VDDMEM are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These pins/balls are not tolerant
to voltages higher than VDDMEM. When using any of the asynchronous memory signals AMS3–2, ARDY, or AOE VDDMEM and VDDEXT must be shorted externally because these
signals are multiplexed with GPIO.
6 The VDDOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent
on voltage and junction temperature) over the lifetime of the part. Please see Table 17 on Page 26 for details.
7 Bidirectional pins/balls (PF15–0, PG15–0, PH7–0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-
BF512/BF514/BF516/BF518(F) are 3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
8 Parameter value applies to all input and bidirectional pins/balls except SDA and SCL.
9 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 11.
10SDA and SCL are pulled up to VBUSTWI. See Table 10.
Rev. PrE | Page 23 of 62 | March 2009