ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
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ADSP-BF512/BF514/BF516/BF518 (F)
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 15 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 15. Absolute Maximum Ratings
Parameter
Rating
Internal Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage1, 2
Input Voltage1, 3
TBD V to +TBD V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to +5.5 V
Output Voltage Swing
Load Capacitance4
– 0.5 V to VDDEXT +0.5 V
200 pF
Storage Temperature Range
–65°C to +150°C
Junction Temperature Underbias
+110ºC
1 Applies to 100% transient duty cycle. For other duty cycles see Table 16.
2 Applies only when VDDEXT is within specifications. When VDDEXT is outside speci-
fications, the range is VDDEXT ± 0.2 Volts.
3 Applies to signals SCL, SDA.
4 For proper SDRAM controller operation, the maximum load capacitance is 50 pF
(at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0,
CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Table 16. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)
TBD
VIN Max (V)
TBD
Maximum Duty Cycle
100 %
TBD
TBD
40%
TBD
TBD
25%
TBD
TBD
15%
TBD
TBD
10%
1 Applies to all signal pins/balls with the exception of CLKIN, XTAL, VROUT.
When programming OTP memory on the ADSP-
BF512/BF514/BF516/BF518(F) processor, the VPPOTP pin/ball
must be set to the write value specified in the Operating Condi-
tions on Page 23. There is a finite amount of cumulative time
that the write voltage may be applied (dependent on voltage and
junction temperature) to VPPOTP over the lifetime of the part.
Therefore, maximum OTP memory programming time for the
processor is shown in Table 17.
Table 17. Maximum OTP Memory Programming Time
VPPOTP Voltage (V) 25°C
6.9
TBD sec
7.0
2400 sec
7.1
1000 sec
Temperature
85°C 110°C 125°C
TBD sec TBD sec TBD sec
TBD sec TBD sec TBD sec
TBD sec TBD sec TBD sec
Preliminary Technical Data
PACKAGE INFORMATION
The information presented in Figure 6 and Table 18 provides
details about the package branding for the processor. For a com-
plete listing of product availability, see Ordering Guide on
Page 62.
a
ADSP-BF51x
tppZccc
vvvvvv.x n.n
#yyww country_of_origin
B
Figure 6. Product Information on Package
Table 18. Package Brand Information
Brand Key
ADSP-BF51x
t
pp
Z
ccc
vvvvvv.x
n.n
#
yyww
Field Description
Product Name
Temperature Range
Package Type
Lead Free Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliance Designator
Date Code
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. PrE | Page 26 of 62 | March 2009
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