ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
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ADSP-BF512/BF514/BF516/BF518 (F)
Preliminary Technical Data
SDRAM Interface Timing
Table 22. SDRAM Interface Timing
Parameter
VDDMEM = 1.8 V
Min
Max
VDDMEM = 2.5/3.3 V
Min
Max
Timing Requirements
tSSDAT
Data Setup Before CLKOUT
tHSDAT
Data Hold After CLKOUT
Switching Characteristics
tSCLK
CLKOUT Period1
tSCLKH
CLKOUT Width High
tSCLKL
tDCAD
tHCAD
CLKOUT Width Low
Command, Address, Data Delay After CLKOUT2
Command, Address, Data Hold After CLKOUT2
tDSDAT
Data Disable After CLKOUT
tENSDAT
Data Enable After CLKOUT
1.5
1.5
0.8
0.8
12.5
12.5
2.5
2.5
2.5
2.5
4.4
4.4
1.0
1.0
4.4
4.4
1.0
1.0
1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 14. Package type and reduced supply voltages affect the best-case value listed here.
2 Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
DATA (IN)
DATA (OUT)
COMMAND, ADDRESS
(OUT)
tSSDAT
tSCLK
tSCLKH
tHSDAT
tSCLKL
tENSDAT
tDCAD
tHCAD
tDSDAT
tDCAD
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 10. SDRAM Interface Timing
Rev. PrE | Page 30 of 62 | March 2009
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