ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
| |||
ADSP-BF512/BF514/BF516/BF518 (F)
Preliminary Technical Data
Table 10 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Table 10. TWI_DT Field Selections and VDDEXT/VBUSTWI
TWI_DT
000 (default)
001
010
011
100
101
110
111 (reserved)
VDDEXT Nominal
3.3
1.8
2.5
1.8
3.3
1.8
2.5
–
VBUSTWI Minimum
2.97
1.27
2.97
2.97
4.5
2.25
2.25
–
VBUSTWI Nominal
3.3
1.8
3.3
3.3
5
2.5
2.5
–
VBUSTWI Maximum
3.63
2.35
3.63
3.63
5.5
2.75
2.75
–
Unit
V
V
V
V
V
V
V
–
Table 11 describes the timing requirements for the processor
clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as
not to exceed the maximum core clock and system clock.
Table 13 describes phase-locked loop operating conditions.
Table 11. Core Clock (CCLK) Requirements—400 MHz Speed Grade1
Parameter
Min
Max
Unit
fCCLK
Core Clock Frequency (VDDINT =TBD V Minimum)
400
MHz
fCCLK
Core Clock Frequency (VDDINT =TBD V Minimum)
TBD
MHz
fCCLK
Core Clock Frequency (VDDINT = TBD V Minimum)
TBD
MHz
fCCLK
Core Clock Frequency (VDDINT = TBD V Minimum)
TBD
MHz
fCCLK
Core Clock Frequency (VDDINT = TBD V Minimum)
TBD
MHz
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 6 on Page 26 and can also be seen on the Ordering Guide on Page 62. It stands for the
maximum allowed CCLK frequency at VDDINT = TBD V and the maximum allowed VCO frequency at any supply voltage.
Table 12. Core Clock (CCLK) Requirements—300 MHz Speed Grade1
Parameter
Min
Max
Unit
fCCLK
Core Clock Frequency (VDDINT =TBD V Minimum)
fCCLK
Core Clock Frequency (VDDINT =TBD V Minimum)
fCCLK
Core Clock Frequency (VDDINT = TBD V Minimum)
fCCLK
Core Clock Frequency (VDDINT = TBD V Minimum)
fCCLK
Core Clock Frequency (VDDINT = TBD V Minimum)
300
MHz
TBD
MHz
TBD
MHz
TBD
MHz
TBD
MHz
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 6 on Page 26 and can also be seen on the Ordering Guide on Page 62. It stands for the
maximum allowed CCLK frequency at VDDINT = TBD V and the maximum allowed VCO frequency at any supply voltage.
Table 13. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Speed Grade1 MHz
1 The speed grade of a given part is printed on the chip’s package as shown in Figure 6 on Page 26 and can also be seen on the Ordering Guide on Page 62. It stands for the
maximum allowed CCLK frequency at VDDINT = TBD V and the maximum allowed VCO frequency at any supply voltage.
Table 14. Maximum SCLK Conditions
Parameter1
VDDEXT = 3.3 V, 2.5 V, or 1.8 V Unit
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ TBD V)
80
MHz
fSCLK
CLKOUT/SCLK Frequency (VDDINT < TBD V)
TBD
MHz
1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 22 on Page 30.
Rev. PrE | Page 24 of 62 | March 2009
Share Link: 