ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
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Preliminary Technical Data
ADSP-BF512/BF514/BF516/BF518 (F)
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 19 and Figure 7 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 26, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 400 MHz/80 MHz.
Table 19. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
tCKINL
tCKINH
tBUFDLAY
tWRST
CLKIN Period1
CLKIN Low Pulse2
CLKIN High Pulse2
CLKIN to CLKBUF Delay
RESET Asserted Pulse Width Low3
20.0
100.0
ns
10.0
ns
10.0
ns
10
ns
11 tCKIN
ns
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 11 through Table 14.
2 Applies to bypass mode and non-bypass mode.
3 Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
CLKIN
CLKBUF
tCKIN
tCKINL
tCKINH
tBUFDLAY
tBUFDLAY
RESET
tWRST
Figure 7. Clock and Reset Timing
Rev. PrE | Page 27 of 62 | March 2009
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