ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF516/BF518 (F)

Asynchronous Memory Read Cycle Timing

Table 20. Asynchronous Memory Read Cycle Timing

Parameter

Timing Requirements

tSDAT

DATA15–0 Setup Before CLKOUT

tHDAT

DATA15–0 Hold After CLKOUT

tSARDY

ARDY Setup Before CLKOUT

tHARDY

ARDY Hold After CLKOUT

Switching Characteristics

tDO

Output Delay After CLKOUT1

tHO

Output Hold After CLKOUT 1

1 Output pins/balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

CLKOUT

AMSx

SETUP

2 CYCLES

tDO

PROGRAMMED READ ACCESS

4 CYCLES

Preliminary Technical Data

Min

Max

Unit

2.1

ns

0.8

ns

4.0

ns

0.0

ns

6.0

ns

0.8

ns

ACCESS EXTENDED

3 CYCLES

HOLD

1 CYCLE

tHO

ABE1–0

ADDR19–1

AOE

ARE

ARDY

DATA15–0

ABE, ADDRESS

tDO

tSARDY

tHARDY

tHO

tHARDY

tSARDY

Figure 8. Asynchronous Memory Read Cycle Timing

tSDAT

READ

tHDAT

Rev. PrE | Page 28 of 62 | March 2009

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