OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

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OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

November 2006

Special Function Blocks (continued)

The BSR is a series connection of boundary-scan cells

(BSCs) around the periphery of the IC. Each I/O pad on

There are four ORCA-defined instructions. The PLC

the FPGA, except for CCLK, DONE, and the boundary-

scan rings 1 and 2 (PSR1, PSR2) allow user-defined

scan pins (TCK, TDI, TMS, and TDO), is included in the

internal scan paths using the PLC latches/FFs. The

BSR. The first BSC in the BSR (connected to TDI) is

RAM_Write Enable (RAM_W) instruction allows the

located in the first PIC I/O pad on the left of the top side

user to serially configure the FPGA through TDI. The

RAM_Read Enable (RAM_R) allows the user to read

back RAM contents on TDO after configuration.

S ORCA Boundary-Scan Circuitry

E The ORCA Series boundary-scan circuitry includes a

test access port controller (TAPC), instruction register

(IR), boundary-scan register (BSR), and bypass regis-

IC ter. It also includes circuitry to support the four pre-

defined instructions.

D Figure 49 shows a functional diagram of the boundary-

scan circuitry that is implemented in the ORCA series.

V E The input pins’ (TMS, TCK, and TDI) locations vary

depending on the part, and the output pin is the dedi-

E cated TDO/RD_DATA output pad. Test data in (TDI) is

U the serial input data. Test mode select (TMS) controls

the boundary-scan test access port controller (TAPC).

D IN Test clock (TCK) is the test clock on the board.

of the FPGA (PTA PIC). The BSR proceeds clockwise

around the top, right, bottom, and left sides of the array.

The last BSC in the BSR (connected to TDO) is located

on the top of the left side of the array (PLA3).

The bypass instruction uses a single FF which resyn-

chronizes test data that is not part of the current scan

operation. In a bypass instruction, test data received on

TDI is shifted out of the bypass register to TDO. Since

the BSR (which requires a two FF delay for each pad)

is bypassed, test throughput is increased when devices

that are not part of a test operation are bypassed.

The boundary-scan logic is enabled before and during

configuration. After configuration, a configuration

option determines whether or not boundary-scan logic

is used.

The 32-bit boundary-scan identification register con-

tains the manufacturer’s ID number, unique part num-

ber, and version, but is not implemented in the ORCA

series of FPGAs. If boundary scan is not used, TMS,

TDI, and TCK become user I/Os, and TDO is 3-stated

or used in the readback operation.

T I/O BUFFERS

EC NT VDD

L O TDI

DATA REGISTERS

BOUNDARY-SCAN REGISTER

PSR1 REGISTER (PLCs)

PSR2 REGISTER (PLCs)

CONFIGURATION REGISTER

(RAM_R, RAM_W)

BYPASS REGISTER

DATA

MUX

SE ISC VDD

D TMS

RESET

CLOCK-DR

SHIFT-DR

UPDATE-DR

INSTRUCTION DECODER

INSTRUCTION REGISTER

RESET

CLOCK-IR

SHIFT-IR

UPDATE-IR

M

TDO

U

X

VDD

SELECT

TCK

VDD

TAP

CONTROLLER

PUR

ENABLE

PRGM

5-2840(C).r7

Figure 49. ORCA Series Boundary-Scan Circuitry Functional Diagram

58

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