OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

Special Function Blocks (continued)

ORCA Series 2 FPGAs

S TCK

E TMS

TDI

IC D Figure 52. Instruction Register Scan Timing Diagram

Fig.5.3(F)

V E Boundary-Scan Timing

To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on

E U the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST

instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-

quency allowed for TCK is 10 MHz.

D IN Figure 52 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to

sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is

SELDEICSTCONT clocked into the DUT on the rising edge.

Lattice Semiconductor

61

Share Link: