OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Estimating Power Dissipation (continued)

SDPM). Therefore, the clock power can be calculated

for the four parts using the following equations:

PCLK = [0.69 mW/MHz + (0.38 mW/MHz – Branch)

(20 Branches)

OR2T04A Clock Power

+ (0.022 mW/MHz – PFU) (150 PFUs)

P = [0.29 mW/MHz

+ (0.006 mW/MHz – SMEM_PFU)

(16 SMEM_PFUs)] [40 MHz]

= 427 mW

S PTTL = 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz

x 20%)]

= 57 mW

E PCMOS = 20 x [0.17 mW x 20 MHz x 20%]

= 13 mW

IC POUT = 30 x [(30 pF + 8.8 pF) x (5.25)2 x 20 MHz

D x 20%]

= 128 mW

V E PBID = 16 x [(50 pF + 8.8 pF) x (5.25)2 x 20 MHz

x 20%]

= 104 mW

E U TOTAL = 1.50 W

D IN OR2TxxA

The total operating power dissipated is estimated by

T summing the standby (IDDSB), internal, and external

T power dissipated. The internal and external power is

the power consumed in the PLCs and PICs, respec-

C tively. In general, the standby power is small and may

N be neglected. The total operating power is as follows:

EPT = Σ PPLC + Σ PPIC

O The internal operating power is made up of two parts:

L clock generation and PFU output power. The PFU out-

put power can be estimated based upon the number of

E C PFU outputs switching when driving an average fan-out

of two:

S IS PPFU = 0.08 mW/MHz

For each PFU output that switches, 0.08 mW/MHz

needs to be multiplied times the frequency (in MHz)

D that the output switches. Generally, this can be esti-

+ (0.10 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T04A clock power ≈ 1.8 mW/MHz.

OR2T08A Clock Power

P = [0.31 mW/MHz

+ (0.12 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T08A clock power ≈ 3.2 mW/MHz.

OR2T10A Clock Power

P = [0.32 mW/MHz

+ (0.14 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T10A clock power ≈ 4.0 mW/MHz.

mated by using one-half the clock rate, multiplied by

some activity factor; for example, 20%.

The power dissipated by the clock generation circuitry

is based upon four parts: the fixed clock power, the

power/clock branch row or column, the clock power dis-

sipated in each PFU that uses this particular clock, and

the power from the subset of those PFUs that is config-

ured in either of the two synchronous modes (SSPM or

Lattice Semiconductor

65

Share Link: