OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

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OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Special Function Blocks (continued)

The TAPC generates control signals which allow cap-

ture, shift, and update operations on the instruction and

ORCA Series TAP Controller (TAPC)

data registers. In the capture operation, data is loaded

into the register. In the shift operation, the captured

The ORCA Series TAP controller (TAPC) is a 1149.1

data is shifted out while new data is shifted in. In the

compatible test access port controller. The 16 JTAG

update operation, either the instruction register is

state assignments from the IEEE 1149.1 specification

are used. The TAPC is controlled by TCK and TMS. The

TAPC states are used for loading the IR to allow three

basic functions in testing: providing test stimuli

S (Update-DR), test execution (Run-Test/Idle), and

obtaining test responses (Capture-DR). The TAPC

allows the test host to shift in and out both instructions

E and test data/results. The inputs and outputs of the

TAPC are provided in the table below. The outputs are

primarily the control signals to the instruction register

IC and the data register.

D Table 13. TAP Controller Input/Outputs

V E Symbol I/O

Function

TMS

E U TCK

PUR

D PRGM

IN TRESET

Select

I Test Mode Select

I Test Clock

I Powerup Reset

I BSCAN Reset

O Test Logic Reset

O Select IR (high); Select DR (low)

T Enable

T Capture-DR

Capture-IR

C N Shift-DR

Shift-DR

E Update-DR

SELDISCO Update-IR

O Test Data Out Enable

O Capture/Parallel Load DR

O Capture/Parallel Load IR

O Shift Data Register

O Shift Instruction Register

O Update/Parallel Load DR

O Update/Parallel Load IR

loaded for instruction decode, or the boundary-scan

register is updated for control of outputs.

The test host generates a test by providing input into

the ORCA Series TMS input synchronous with TCK.

This sequences the TAPC through states in order to

perform the desired function on the instruction register

or a data register. Figure 50 provides a diagram of the

state transitions for the TAPC. The next state is deter-

mined by the TMS input value.

1

TEST-LOGIC-

RESET

0

0

RUN-TEST/ 1

IDLE

SELECT- 1

DR-SCAN

SELECT-

1

IR-SCAN

0

1

CAPTURE-DR

0

1

CAPTURE-IR

0

0

SHIFT-DR

0

SHIFT-IR

0

1

1

EXIT1-DR

1

1

EXIT1-IR

0

0

PAUSE-DR

0

PAUSE-IR

0

1

0

EXIT2-DR

1

0

EXIT2-IR

1

1

UPDATE-DR

1

0

UPDATE-IR

1

0

5-5370(F)

Figure 50. TAP Controller State Transition Diagram

Lattice Semiconductor

59

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