OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

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OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

November 2006

Estimating Power Dissipation (continued)

Table 16. DC Power for 5 V Tolerant I/Os for

OR2TxxA devices

OR2T15A Clock Power

Device

PTOL (VDD5 = 5.25 V)

P = [0.34 mW/MHz

2T04A

1.7 mW

+ (0.17 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

S For a quick estimate, the worst-case (typical circuit)

OR2T15A clock power ≈ 5.9 mW/MHz.

E OR2T26A Clock Power

P = [0.35 mW/MHz

+ (0.19 mW/MHz – Branch) (# Branches)

IC + (0.01 mW/MHz – PFU) (# PFUs)

D + (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

V For a quick estimate, the worst-case (typical circuit)

E OR2T26A clock power ≈ 8.3 mW/MHz.

E OR2T40A Clock Power

U P = [0.37 mW/MHz

+ (0.23 mW/MHz – Branch) (# Branches)

D IN + (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

T T For a quick estimate, the worst-case (typical circuit)

OR2T40A clock power ≈ 12.4 mW/MHz.

C The power dissipated in a PIC is the sum of the power

N dissipated in the four I/Os in the PIC. This consists of

power dissipated by inputs and ac power dissipated by

E outputs. The power dissipated in each I/O depends on

O whether it is configured as an input, output, or input/

output. If an I/O is operating as an output, then there is

L a power dissipation component for PIN, as well as

E C POUT. This is because the output feeds back to the

input.

The power dissipated by an input buffer (VIH = VDD –

S IS 0.3 V or higher) is estimated as:

PIN = 0.09 mW/MHz

D The 5 V tolerant input buffer feature dissipates addi-

2T08A

2T10A

2T15A

2T26A

2T40A

2.4 mW

2.7 mW

3.4 mW

4.0 mW

5.0 mW

The ac power dissipation from an output or bidirec-

tional is estimated by the following:

POUT = (CL + 8.8 pF) x VDD2 x F Watts

where the unit for CL is farads, and the unit for F is Hz.

As an example of estimating power dissipation,

suppose that a fully utilized OR2T15A has an average

of three outputs for each of the 400 PFUs, that all

20 clock branches are used, that 150 of the 400 PFUs

have FFs clocked at 40 MHz (16 of which are operating

in a synchronous memory mode), and that the PFU

outputs have an average activity factor of 20%.

Twenty inputs, 32 outputs driving 30 pF loads, and

16 bidirectional I/Os driving 50 pF loads are also gen-

erated from the 40 MHz clock with an average activity

factor of 20%. The worst-case (VDD = 3.6 V) power dis-

sipation is estimated as follows:

PPFU = 400 x 3 (0.08 mW/MHz x 20 MHz x 20%)

= 384 mW

PCLK

= [0.34 mW/MHz + (0.17 mW/MHz – Branch)

(20 Branches)

+ (0.01 mW/MHz – PFU) (150 PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(16 SMEM_PFUs)] [40 MHz]

= 212 mW

PIN = 20 x [0.09 mW/MHz x 20 MHz x 20%]

= 7 mW

PTOL = 3.4 mW

POUT = 30 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz

x 20%]

tional dc power. The dc power, PTOL, is always dissi-

pated for the OR2TxxA, regardless of the number of

= 60 mW

5 V tolerant input buffers used when the VDD5 pins are PBID = 16 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz

connected to a 5 V supply as shown in Table 16. This

x 20%]

power is not dissipated when the VDD5 pins are con-

nected to the 3.3 V supply.

= 49 mW

TOTAL = 0.72 W

66

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