ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices
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ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Master Timing
Table 41 and Figure 26 describe SPI port master operations.
Table 41. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data
Input Setup)
tHSPIDM SCK Sampling Edge to Data Input
Invalid
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tDDSPIDM
SPISELx low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data
Out Delay)
tHDSPIDM SCK Edge to Data Out Invalid (Data
Out Hold)
ADSP-BF522/524/526
VDDEXT = 1.8 V
VDDEXT = 2.5/3.3 V
Min
Max
Min
Max
11.6
11.6
–1.5
–1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
6
6
–1.0
–1.0
ADSP-BF523/525/527
VDDEXT = 1.8 V
VDDEXT = 2.5/3.3 V
Min
Max
Min
Max Unit
11.6
9.6
ns
–1.5
–1.5
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
4 × tSCLK – 1.5
4 × tSCLK – 1.5
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
6
6 ns
–1.0
–1.0
ns
SPISELx
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tHDSPIDM
MOSI
(OUTPUT)
MSB
CPHA = 1
MISO
(INPUT)
MSB VALID
tHDSPIDM
MOSI
(OUTPUT)
MSB
CPHA = 0
MISO
(INPUT)
tSSPIDM
tHSPIDM
MSB VALID
tSPICLK
tHDSM
tSPITDM
tDDSPIDM
LSB
tSSPIDM
tHSPIDM
LSB VALID
tDDSPIDM
LSB
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrG | Page 52 of 80 | February 2009
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