ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices
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ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
HOSTDP A/C Timing- Host Read Cycle
Table 48 describe the HOSTDP A/C Host Read Cycle timing
requirements.
Table 48. Host Read Cycle Timing Requirements
ADSP-BF522/524/526,
ADSP-BF523/525/527
Parameter
Timing Requirements
tSADRDL HOST_ADDR and HOST_CE Setup
before HOST_RD falling edge
VDDEXT = 1.8 V
Min
Max
4
VDDEXT = 2.5/3.3 V
Min
Max
4
VDDEXT = 1.8 V
Min
Max
4
VDDEXT = 2.5/3.3 V
Min
Max Unit
4
ns
tHADRDH
tRDWL
tRDWL
tRDWH
tDRDHRDY
HOST_ADDR and HOST_CE Hold
2.5
after HOST_RD rising edge
HOST_RD pulse width low
(ACK mode)
HOST_RD pulse width low
(INT mode)
tDRDYRDL +
tRDYPRD +
tDRDHRDY
1.5 × tSCLK
+ 8.7
HOST_RD pulse width high or time 2 × tSCLK
between HOST_RD rising edge and
HOST_WR falling edge
HOST_RD rising edge delay after
0
HOST_ACK rising edge (ACK mode)
2.5
tDRDYRDL +
tRDYPRD +
tDRDHRDY
1.5 × tSCLK
+ 8.7
2 × tSCLK
0
2.5
tDRDYRDL +
tRDYPRD +
tDRDHRDY
1.5 × tSCLK
+ 8.7
2 × tSCLK
0
2.5
ns
tDRDYRDL +
ns
tRDYPRD +
tDRDHRDY
1.5 × tSCLK
ns
+ 8.7
2 × tSCLK
ns
0
ns
Switching Characteristics
tSDATRDY Data valid prior HOST_ACK rising
edge (ACK mode)
tDRDYRDL Host_ACK assertion delay after
HOST_RD/HOST_CE (ACK mode)
tRDYPRD HOST_ACK low pulse-width for
Read access (ACK mode)
tDDARWH Data disable after HOST_RD
tACC
Data valid after HOST_RD falling
edge (INT mode)
4.5
3.5
4.5
3.5
ns
1.5 × tSCLK
NM1
1.5 × tSCLK
NM1
1.5 × tSCLK
NM1
1.5 × tSCLK ns
NM1 ns
9.0
1.5 × tSCLK
9.0
1.5 × tSCLK
9.0
1.5 × tSCLK
9.0 ns
1.5 × tSCLK ns
tHDARWH Data hold after HOST_RD rising
1.0
1.0
1.0
1.0
ns
edge
1 NM (Not Measured) — This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.
HOST_ADDR
HOST_CE
HOST_RD
tSADRDL
tRDWL
tHADRDH
tRDWH
HOST_ACK
HOST_D15-0
tDRDYRDL
tRDYPRD
tDRDHRDY
tSDATRDY
tACC
tHDARWH
Figure 33. HOSTDP A/C- Host Read Cycle
tDDARWH
Rev. PrG | Page 58 of 80 | February 2009
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