ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices

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ADSP-BF526BBCZ-4AX

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

Timer Clock Timing

Table 46 and Figure 31 describe timer clock timing.

Table 46. Timer Clock Timing

Parameter

Switching Characteristic

tTODP

Timer Output Update Delay After PPI_CLK High

ADSP-BF522/523/524/525/526/527

VDDEXT = 1.8 V

Min

Max

12.0

VDDEXT = 2.5/3.3 V

Min

Max

Unit

12.0 ns

PPI_CLK

TMRx OUTPUT

tTODP

Figure 31. Timer Clock Timing

Up/Down Counter/Rotary Encoder Timing

Table 47. Up/Down Counter/Rotary Encoder Timing

Parameter

VDDEXT = 1.8 V

Min

Max

Timing Requirements

tWCOUNT

tCIS

tCIH

Up/Down Counter/Rotary Encoder Input Pulse Width

Counter Input Setup Time Before CLKOUT Low1

Counter Input Hold Time After CLKOUT Low1

tSCLK + 1

4.0

4.0

1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

VDDEXT = 2.5/3.3 V

Min

Max

Unit

tSCLK + 1

ns

4.0

ns

4.0

ns

CLK OUT

CUD/CDG/CZM

tCIS

tCIH

tWCOUNT

Figure 32. Up/Down Counter/Rotary Encoder Timing

Rev. PrG | Page 57 of 80 | February 2009

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