ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices

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ADSP-BF526BBCZ-4AX

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Timer Cycle Timing

Table 45 and Figure 30 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (fSCLK/2) MHz.

Table 45. Timer Cycle Timing

ADSP-BF522/524/526

ADSP-BF523/525/527

Parameter

VDDEXT = 1.8 V

Min

Max

VDDEXT = 2.5/3.3 V

Min

Max

VDDEXT = 1.8 V

Min

Max

VDDEXT = 2.5/3.3 V

Min

Max Unit

Timing Characteristics

tWL

Timer Pulse Width Input

tSCLK

tSCLK

tSCLK

tSCLK

ns

Low (Measured In SCLK

Cycles)1

tWH

Timer Pulse Width Input

tSCLK

tSCLK

tSCLK

tSCLK

ns

High (Measured In SCLK

Cycles)1

tTIS

Timer Input Setup Time

5

Before CLKOUT Low2

5

8.1

6.2

ns

tTIH

Timer Input Hold Time

–2

–2

–2

–2

ns

After CLKOUT Low2

Switching Characteristics

tHTO

Timer Pulse Width Output tSCLK (232–1)tSCLK tSCLK (232–1)tSCLK tSCLK–1 (232–1)tSCLK tSCLK–1 (232–1)tSCLK ns

(Measured In SCLK Cycles)

tTOD

Timer Output Update

8.1

8.1

6

Delay After CLKOUT High

6 ns

1 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.

2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

CLKOUT

TMRX OUTPUT

TMRx INPUT

tTIS

tTIH

tWH, tWL

Figure 30. Timer Cycle Timing

tTOD

tHTO

Rev. PrG | Page 56 of 80 | February 2009

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