ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices
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ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 42 and Figure 27 describe SPI port slave operations.
Table 42. Serial Peripheral Interface (SPI) Port—Slave Timing
ADSP-BF522/524/526
ADSP-BF523/525/527
Parameter
VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V
Min Max Min Max
VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V
Min Max Min Max Unit
Timing Requirements
tSPICHS Serial Clock High Period
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK –1.5
2 × tSCLK – 1.5
ns
tSPICLS Serial Clock Low Period
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK –1.5
2 × tSCLK – 1.5
ns
tSPICLK Serial Clock Period
4×
tSCLK – 1.5
4×
tSCLK – 1.5
4×
tSCLK – 1.5
4×
ns
tSCLK – 1.5
tHDS
Last SCK Edge to SPISS Not Asserted
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK –1.5
2 × tSCLK – 1.5
ns
tSPITDS Sequential Transfer Delay
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK –1.5
2 × tSCLK – 1.5
ns
tSDSCI SPISS Assertion to First SCK Edge
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK –1.5
2 × tSCLK – 1.5
ns
tSSPID Data Input Valid to SCK Edge (Data Input
1.6
1.6
1.6
1.6
ns
Setup)
tHSPID SCK Sampling Edge to Data Input Invalid
1.6
1.6
1.6
1.6
ns
Switching Characteristics
tDSOE SPISS Assertion to Data Out Active
0
12.0
0
12.0
0
12.0
0
10.3 ns
tDSDHI SPISS Deassertion to Data High Impedance
0
8.5
0
8.5
0
8.5
0
8 ns
tDDSPID SCK Edge to Data Out Valid (Data Out Delay)
10
10
10
10 ns
tHDSPID SCK Edge to Data Out Invalid (Data Out
0
0
0
0
ns
Hold)
SPISS
(INPUT)
SCKx
(CPOL = 0)
(INPUT)
SCKx
(CPOL = 1)
(INPUT)
MISOx
(OUTPUT)
tSPICHS
tSPICLS
tSDSCI
tSPICLS
tSPICHS
tDSOE
tDDSPID
tHDSPID
MSB
CPHA = 1
MOSIx
(INPUT)
tSSPID
tHSPID
MSB VALID
tDSOE
tHDSPID
MISOx
(OUTPUT)
MSB
CPHA = 0
MOSIx
(INPUT)
MSB VALID
tSPICLK
tHDS
tSPITDS
tDDSPID
tDSDHI
LSB
LSB VALID
tDDSPID
tDSDHI
LSB
tSSPID
tHSPID
LSB VALID
Figure 27. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrG | Page 53 of 80 | February 2009
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