ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
| |||
Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
HOSTDP A/C Timing- Host Write Cycle
Table 49 describes the HOSTDP A/C Host Write Cycle timing
requirements.
Table 49. Host Write Cycle Timing Requirements
ADSP-BF522/524/526
ADSP-BF523/525/527
Parameter
Timing Requirements
tSADWRL HOST_ADDR/HOST_CE Setup
before HOST_WR falling edge
VDDEXT = 1.8 V
Min
Max
4
VDDEXT = 2.5/3.3 V
Min
Max
4
VDDEXT = 1.8 V
Min
Max
4
VDDEXT = 2.5/3.3 V
Min
Max Unit
4
ns
tHADWRH
tWRWL
HOST_ADDR/HOST_CE Hold
after HOST_WR rising edge
HOST_WR pulse width low
(ACK mode)
tWRWH
HOST_WR pulse width low
(INT mode)
HOST_WR pulse width high
or time between HOST_WR
rising edge and HOST_RD
falling edge
2.5
tDRDYWRL +
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
+ 8.7
2 × tSCLK
2.5
tDRDYWRL +
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
+ 8.7
2 × tSCLK
2.5
tDRDYWRL +
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
+ 8.7
2 × tSCLK
2.5
ns
tDRDYWRL +
ns
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
ns
+ 8.7
2 × tSCLK
ns
tDWRHRDY HOST_WR rising edge delay
after HOST_ACK rising edge
(ACK mode)
tHDATWH Data Hold after HOST_WR
rising edge
tSDATWH Data Setup before HOST_WR
rising edge
Switching Characteristics
tDRDYWRL HOST_ACK low delay after
HOST_WR/HOST_CE asserted
(ACK mode)
tRDYPWR HOST_ACK low pulse-width for
Write access (ACK mode)
0
0
0
0
ns
2.5
2.5
2.5
2.5
ns
2.5
2.5
2.5
2.5
ns
1.5 × tSCLK
NM1
1.5 × tSCLK
NM1
1.5 × tSCLK
NM1
1.5 × tSCLK ns
NM1 ns
1 NM (Not Measured) — This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.
HOST_ADDR
HOST_CE
HOST_WR
tSADWRL
tWRWL
tHADWRH
tWRWH
HOST_ACK
HOST_D15-0
tDRDYWRL
tRDYPWR
tSDATWH
tDWRHRDY
tHDATWH
Figure 34. HOSTDP A/C- Host Write Cycle
Rev. PrG | Page 59 of 80 | February 2009
Share Link: 