CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.3
KBDCR (0x08) — Keyboard Control
76543210
T TRREPDC
T
R
E
P
D
C
Write
Read
transmit status
receive status
enable
received parity
data pin status
clock pin status
bits[7:4, 2] ignored
bit[3] enable:
0
state machine cleared
1
state machine enabled
bit[1] force KBDATA pin low:
0
don't force low
1
force low
bit[0] force KBCLK pin low:
0
don't force low
1
force low
bit[7] TXE shift register empty:
0
not ready
1
enabled and ready to transmit
bit[6] TXB, transmitter busy:
0
not busy
1
currently sending data
bit[5] RXF, receive shift register full:
0
not full
1
ready to read
bit[4] RXB, receiver busy:
0
not busy
1
currently receiving data
bit[3] ENA, state machine enable:
0
disabled
1
enabled
bit[2] RXP, receive parity bit, odd parity bit for last received data
bit[1] SKD, KBDATA pin value after synchronization
bit[0] SKC, KBCLK pin value after synchronization
82
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
June 1997