CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.8

SUSMODE (0x1C) — SUSPEND Mode

76543210

XXXXXXXS

This register allows the CPU to set the CL-PS7500FE into SUSPEND mode. Only one bit (0) is used, and

a write to this bit causes SUSPEND mode to be entered. The value written to bit 0 determines if the exter-

nal I/O clocks, normally output from the device, are also disabled during SUSPEND mode. The value pro-

grammed depends on the peripherals being driven by these clocks.

S

SUSPEND mode control of external I/O clocks.

Enter SUSPEND mode with MEMCLK, FCLK, I/O clocks, and some internal

clocks stopped. DMA continues and the write to this location completes on

either wakeup event, nIRQ or nFIQ or reset.

Write

turn off external I/O clocks when in this mode

0

turn off

1

do not turn off

Read

return above value

Reset

set to ‘0’

10.3.9

IRQSTB (0x20) — IRQ B Interrupts Status

76543210

K J PT I SCF

K

J

P

T

I

S

C

F

Write

Read

keyboard receive interrupt

keyboard transmit interrupt

nINT3, active-low

nINT4, active-low

INT5, active-high

nINT6, active-low

INT7, active-high

nINT8, active-low

ignored

status

0

1

inactive

active

June 1997

ADVANCE DATA BOOK v2.0

85

MEMORY AND I/O PROGRAMMERS’ MODEL

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