CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.17 T0low (0x40) — Timer 0 Low Bits

76543210

LLLLLLLL

There are eight registers associated with the two 16-bit timers in CL-PS7500FE.

L

low byte of timer

Write

set low byte latch value that is loaded into timer when it reaches end count

Read

read value of low count latched by the ‘Latch’ command T0LAT

10.3.18 T0high (0x44) — Timer 0 High Bits

76543210

HHHHHHHH

H

Write

Read

high byte of timer

set high byte latch value that is loaded into timer when it reaches end count

read value of high count latched by the ‘Latch’ command T0LAT

10.3.19 T0GO (0x48) — Timer 0 Go Command

Write

load counter with high and low latch values and start to decrement (value

ignored)

Read

ignored

10.3.20 T0LAT (0x4C) — Timer 0 Latch Command

Write

latch timer value in high and low count latches (value ignored)

Read

ignored

10.3.21 T1low (0x50) — Timer 1 Low Bits

76543210

LLLLLLLL

L

Write

Read

low byte of timer

set low byte latch value loaded into timer when it reaches end count

read value of low count latched by the ‘Latch’ command T1LAT

10.3.22 T1high (0x54) — Timer 1 High Bits

76543210

HHHHHHHH

H

Write

Read

high byte of timer

set high byte latch value that is loaded into timer when it reaches end count

read value of high count latched by the ‘Latch’ command T1LAT

June 1997

ADVANCE DATA BOOK v2.0

89

MEMORY AND I/O PROGRAMMERS’ MODEL

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