CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.4
IOLINES (0x0C) — IOP[7:0] Port Control
76543210
IIIIIIII
This register is the control for the 8-bit I/O port included in the CL-PS7500FE. Each bit independently con-
trols the state of one of the open drain I/O pins IOP[7:0]. On reset, all the bits are configured to be inputs.
I
IOP open drain pin
Write
corresponding pin:
0
force corresponding pin low
1
corresponding pin becomes an input
Read
read value on corresponding pin
Reset
set all as inputs
10.3.5
IRQSTA (0x10) — IRQ A Interrupts Status
76543210
1 TURFN0 P
This is the first of four sets of IRQ interrupt control, masking and status registers in CL-PS7500FE. Not
all the bits in each register are used. Note that this status register contains a bit (7) that is always active,
and can force an interrupt from software by programming the corresponding bit in the IRQA mask register
high.
1
always active bit
T
2-MHz timer 1, rising-edge triggered
U
2-MHz timer 0, rising-edge triggered
R
power on reset
F
FLYBACK, rising-edge triggered
N
nINT1, falling-edge triggered
P
INT2, rising-edge triggered
Write
ignored
Read
status
bit[7] is always ‘1’
bits[6:2, 0]
0
not triggered since last cleared
1
triggered since last cleared
bit[1] is always 0
Reset
clear bits[6:5, 3:2, 0] to ‘0’
power on reset sets bit[4] to ‘1’
push button reset maintains the current bit[4] value
June 1997
ADVANCE DATA BOOK v2.0
83
MEMORY AND I/O PROGRAMMERS’ MODEL
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