CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.6
IRQRQA (0x14) — IRQ A Interrupts Request/Clear
76543210
1 TURFNXP
1
T
U
R
F
N
P
Write
Read
always active bit
2-MHz timer 1, rising-edge triggered
2-MHz timer 0, rising-edge triggered
power on reset
FLYBACK, rising edge triggered
nINT1, falling-edge triggered
INT2, rising-edge triggered
clear triggered interrupts
0
do not clear interrupt
1
clear interrupt
requests, as status, but bitwise AND’ed with mask
10.3.7 IRQMSKA (0x18) — IRQ A Interrupts Mask
76543210
1 TURFN0 P
1
T
U
R
F
N
P
Write
Read
Reset
always active bit
2-MHz timer 1, rising-edge triggered
2-MHz timer 0, rising-edge triggered
power on reset
FLYBACK, rising-edge triggered
nINT1, falling-edge triggered
INT2, rising-edge triggered
set mask for each interrupt source
0
do not form part of nIRQ
1
form part of nIRQ
value set by write
set all ‘0’ (none affect nIRQ)
84
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
June 1997